Senior Communication IP Lead
Enable scalable low-latency network-on-chip architecture for zetta-scale HPC/AI system
SectorElectronics & Engineering
What you will do
The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.
The CSA team is looking for a senior communications IP architect within the hardware team. With you, we are going to enable the communication IP needed for the efficient execution of workloads in a zetta-scale computing system. You will be responsible for designing and modeling high-performance uncore and network-on-chip architectures across the breadth of heterogeneous core complex portfolio. Hierarchical cluster architectures are essential to producing high-performance multicore architectures that can scale to 1000+ cores. This architect will work with a team for the development of such highly scalable multicore architectures. You should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.
You are motivated by an experience within an industrial research startup unit with fast growth and high visibility, having access to top notch silicon technology (beyond 7nm), team of technical experts from multiple domains interested in true hw-sw codesign, all in a very competitive international environment.
- Model Uncore & NoC Architecture. As the Uncore & NoC Modeler, you will be responsible for the performance modeling of various aspects of high-performance uncore & NoC architectures. Examples include the modeling core-to-core coherence protocols and interconnects, cluster architecture, shared cluster and system cache architectures, and interaction with memory system.
- Act as a key person in developing the upcoming RISC-V platforms, which will connect numerous cores together on a chip, support large bandwidth, as well as new applications and workloads
- If interested, you will have a unique opportunity to analyze market verticals and design architectures specifically tailored for upcoming use cases.
- Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip.
- Familiarity with ARM GIC architecture and interrupt routing mechanisms.
- Strong working knowledge of architecture tradeoff analysis and performance trouble shooting.
- Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools.
- Ability to define bus components micro-architecture while taking into account performance/power/area tradeoff.
- Ability to quickly react and adapt to changes.
- Excellent communication skills.
- Familiarity with CPU/GPU architecture is a big plus
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. In everything we do, your future colleagues are guided by the imec values of passion, excellence, connectedness and integrity. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
This is your opportunity to define and help drive imec’s system architecture roadmap to build the AI technology of the near and far away future.
This is your chance to help define and drive imec’s system architecture roadmap to build the AI technology of the near and far away future.
Who you are
- 3+ years of experience in uncore & NoC architecture modeling.
- MS or PhD in computer architecture.
- Strong ability to comprehend various architectural ingredients, such as virtualization, security, power management, and others, when architecting the uncore & NoC components.
- Experience with uncore & NoC design flow, including spec definition, architecture design, and performance modeling.
- Familiarity with advanced CPU architectures and pipelines, coherence protocols, interconnect architectures, and system architectures.
- Extensive experience in designing and integrating communication centric IPs within complex SoCs.
- Strong understanding of hardware design, timing analysis, clock domain crossing, lint and verification.
- Experience in IP, Algorithm Model development using C/C++/SystemC.
- You are a constructive team player and actively share experience and knowledge with colleagues.
- Your networking skills, creativity, persistence, and passion for what you do are highly valued.
- We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.
How can we help?
The Leuven MindGate team is at your disposal for any questions about the Leuven Innovation Region. Do you want to invest, work or study in the region? We can help you find your way.
We also facilitate collaboration and innovation between companies, knowledge institutes and government within the Leuven Innovation Region, and we are happy to guide any of these stakeholders towards innovation.