PostDoc: Optimizing Parallel Graph Algorithms with Computation near Memory

What you will do

Processing large graphs at scale forms an emerging workload for a variety of problems, including social network analysis, robotic path planning, optimization, etc. Traditionally, disk parallel algorithms are used to handle the huge volumes of graph data. New hardware architectures with compute near memory unlock new opportunities to reduce the overhead of data transfers between the disk and the compute cores. Another option could be to leverage computation near or within main memory or storage class memory.
The fundamental challenge is to find an efficient partitioning of the data and the computation across the different levels of memory and compute hierarchies, to optimize power, cost and performance of the targeted graph applications. To explore such an optimization path, a framework needs to build to assess the benefits of the technology solutions at the system level. The broad goal is to have a system simulation and optimization framework that can help to explore the benefits of architecture aware mapping solutions for parallel graph algorithms, to obtain the PPAC (Power Performance Area Cost) benefits at the system level. Parts of the solution exist, but no complete framework has become available in the research community yet. It will be crucial to strike the right balance between modelling detail, flexibility, and exploration run-time.
In this post doc, you will develop or extend a system-level modelling framework to model different levels of memory and compute hierarchy. Further, your work will look into parallel graph algorithms to identify bottlenecks and to propose novel mapping techniques to alleviate the identified bottlenecks using innovative architectural choices. The proposed framework should be scalable, and capable of evaluating the PPAC of the algorithms mapped onto the target architectures on the largest publicly-available graphs. You will work closely within the imec Compute System Architecture (CSA) unit at imec Leuven, and our various academic and industrial collaborators.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You have a Ph.D. degree in Electrical or Computer Engineering preferably focusing on the compute near storage or compute near memory
• You have experience with computer architectures
• Experience in co-design of software and hardware is a plus.
• You are aware of traditional memory subsystem organization and next generations of memory technology.
• We value your experience with system modelling tools and languages: SystemC, Gem5 or similar.
• Familiarity with graph algorithms is a plus.
• Familiarity with mapping new algorithms to architectures is a plus.
• You are a constructive team player and actively share experience and knowledge with colleagues.
• Your networking skills, creativity, persistence and passion for what you do are highly valued.
• We are looking for your excellent communication skills in English, as you will work in a multicultural team and interact with our collaborators.