DFT Architect

What you will do

• Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft/hard IPs with complex DFT requirements.
• Coordinate/Negotiate DFT requirements with the project teams and the customers.
• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/R(epair), OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues.
• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.
• Work closely with the test engineering team on silicon characterization and validation.
  
  

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• 15+ years of experience in digital ASIC design, 10+ years of experience with DFT insertion and ATPG.
• Basic fluency with Verilog/VHDL to write code for test logic when needed.
• Experience as a DFT lead defining chip- and block-level DFT specifications in at least one project with hierarchical DFT.
• Hands-on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, Test debug, for large low-power designs in advanced nodes (7nm and beyond).
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).
• Preferably previous experience with defining a DFT flow.
• Experienced in EDA tools such as Genus/Modus (Cadence) and Tessent (Siemens), and simulation tools.
• Experience using Tessent SSN is a plus.
• Experienced in scripting languages especially TCL.