PhD project


11 March 2019

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For more information please contact Prof. dr. ir. Georges Gielen, tel.: +32 16 324076, mail:

You can apply for this job no later than April 15, 2019 via the online application tool
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Apply before 15 April 2019

This PhD project will take place in collaboration between imec and the ESAT-MICAS (Microelectronics and Sensors) research group of the Department of Electrical Engineering (ESAT) of the KU Leuven. Academic supervisors will be Prof. Georges Gielen and Prof. Guido Groeseneken.

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Several new directions have been pursued by the semiconductor industry in the past decade. In Field Effect Transistors (FETs) :

1) conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates;

2) new transistorar chitectures are being introduced, ranging from FinFETs to nanowire and nanosheet FETs;

3) transistors are downscaled toward atomic dimensions with each stochastically-behaving gate oxide defect potentially having a substantial impact on the device operation;

while iv) supply voltages are reduced; nonetheless, the electric fields are increasing.

All of these developments constitute new challenges for ensuring sufficient reliability, i.e., limited degradation during operation, of the FETs based on such advanced CMOS VLSI technologies. Thorough physics-based models are already being developed for the various degradation mechanisms (such as Bias Temperature Instability, Hot Carrier Degradation, etc.) occurring in different regions of the FET {Vgate, Vdrain} operating space. These mechanisms include charging of preexisting defects in the gate dielectrics and simultaneous generation of new defects, e.g. by hot carriers, compounded by significant channel temperature increases due to FET "self-heating".

However, to understand the impact of the degradation on circuits, the existing physical insights need to be converted to compact models usable in SPICE-level circuit simulations. The PhD project therefore encompasses:

1) converting the already-developed physical models into such reliability-aware compact models, able to describe the degradation (both mean and variation) of all major FET parameters, such as Vth, gm, SS, Id,lin, Id,sat,etc., in the entire {Vgate, Vdrain}} operating space as a function of an arbitrary stress history;

2) enabling the simulation of FET degradation in various analog and digital circuits and understanding the implications for various circuit parameters;

and 3) carrying out the design, layout, and measurement of test circuits to validate the developed compact models and the simulation methodology. 

The PhD researcher will develop compact mathematical descriptions of degradation in state-of-the-art VLSI devices, design and lay out circuits, and simulate and measure their reliable operation for various mission scenarios.


Required background: Master in Electrical Engineering or Master in Nanoengineering/Nanotechnology, with expertise in IC design and nanotechnology.

Detailed background knowledge : semiconductor device physics, transistor-level circuit simulations, transistor-level circuit design, layout, and electrical measurements.


The position offers a PhD scholarship for 4 years.

When applying for this PhD position, the applicant must SIMULTANEOUSLY apply for scholarship funding at the following website :

by the deadline indicated on this website.