For more information please contact Prof. dr. ir. Georges Gielen, tel.: +32 16 324076, mail: firstname.lastname@example.org
You can apply for this job no later than April 15, 2019 via the online application tool
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This PhD project will take place in collaboration between imec and the ESAT-MICAS (Microelectronics and Sensors) research group of the Department of Electrical Engineering (ESAT) of the KU Leuven. Academic supervisors will be Prof. Georges Gielen and Prof. Chris Van Hoof.
The brain is the most complex organ in the human body and, to be able to understand how it works, large-scale in-vivo sensing of neuron populations has emerged as a key research technique. Microfabricated silicon neural probes have been established as the dominant technology in this field and have achieved ever increasing densities and numbers of simultaneous recording electrodes. imec is the leader in the design and development of CMOS neural probes that achieve minimum probe-shank dimensions, high electrode density and large number of simultaneous recording channels with low-noise and low-power performances. With these probes, it is currently possible to record from many neurons spanning multiple brain regions. However, future neural probes will require even higher numbers of simultaneous recording sites to enable the study of much larger neuron populations in the brain. In addition, wireless data transmission is becoming an important requirement to allow experiments with free-moving animals without tethering cables. Thus, on-chip neural signal processing is compulsory in such system to compress the enormous raw data which take way too much power to be transmitted wirelessly. The ideal solution would be to sort the recorded neural spikes before transmission, so that only the identifiers of the recorded neurons and their spike timings need to be transmitted.
The essential challenge for realizing such system is to find ultra-low-power solutions to implement spike sorting algorithms on chip. The power consumed by the spike sorting circuits needs to be less than the power saved in wireless data transmission. This PhD research aims to tackle this challenge based on two primary hypotheses:
Hypothesis 1: The power efficiency of spike sorting circuits can be improved by taking a hybrid analog-digital computation approach.
The conventional system approach consists of a low-noise analog front-end and a high-precision analog-to-digital converter on the recording ASIC, and a spike sorting algorithm implemented on an external digital signal processor. This approach is optimal for spike sorting accuracy and algorithm flexibility, but not for power efficiency. In particular, we hypothesize the following improvements:
Hypothesis 1.1: A significant part of the signal processing and computation in spike sorting algorithms can be implemented using reduced-precision low-power analog circuitry (e.g. log-domain NEO-based neural detector, switched-capacitor-based matrix multiplier for feature extraction, etc.).
Hypothesis 1.2: Analog preprocessing can improve system power efficiency by reducing the data redundancy before spike sorting (e.g. spike-triggered sampling, adaptive ADC resolution, compressed sensing).
Hypothesis 2: A significant reduction in power consumption can be achieved by implementing application-specific instead of general-purpose spike sorting algorithms on chip.
Many brain-machine interface applications may not require the recorded neural signals to be sorted. For example, multi-unity activity (sample-by-sample RMS of AP signals recorded from multiple unsorted neurons) has been demonstrated to be sufficient for arm movement prediction. There are also many algorithms that demonstrate comparable neural decoding performance omitting several intermediate spike sorting steps. Those application-specific algorithms are less power hungry and are suitable for on-chip integration.
This PhD research will focus on developing and designing hardware-efficient neural signal processors based on hybrid analog/digital computation. The PhD researcher will explore new low-power analog circuits to implement neural feature extraction. The student will then design and implement these architectures in an ASIC, and test the functionality and performance in a real-case scenario.
Required background: Master in Electrical Engineering with focus on analog or mixed-signal CMOS IC design.
The position offers a PhD scholarship for 4 years.
When applying for this PhD position, the applicant must SIMULTANEOUSLY apply for scholarship funding at the following website :
by the deadline indicated on this website.